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Results 1 to 25 of 967

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Exploring the effectiveness of various patterns in an extended pattern search layout algorithmSU YIN; CAGAN, Jonathan.Journal of mechanical design (1990). 2004, Vol 126, Num 1, pp 22-28, issn 1050-0472, 7 p.Article

Balancing electrical and optical interconnection resources at low levelsDRABIK, T. J.SPIE proceedings series. 1998, pp 556-559, isbn 0-8194-2949-XConference Paper

Geometrical figure processing for IC layout extracted from silicon die imageJONG, C. C; TAN, O. K; SING, S. C et al.International journal of electronics. 1995, Vol 78, Num 2, pp 367-394, issn 0020-7217Article

Partitioning algorithms for layout synthesis from register-transfer netlistsWU, A. C.-H; GAJSKI, D. D.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 4, pp 453-463, issn 0278-0070Article

Three-layer channel routingYUN KANG CHEN; MEI LUN LIU.IEEE transactions on computer-aided design of integrated circuits and systems. 1984, Vol 3, Num 2, pp 156-163, issn 0278-0070Article

Optimales Layout durch richtigen Autorouter-Einsatz = Optimal design by the use of the right routerSCHINNERL, C.F & M. Feinwerktechnik, Mikrotechnik, Messtechnik. 1995, Vol 103, Num 7-8, pp 404-407, issn 0944-1018Article

A fast, single-layer, area router for semi-custom analogue circuitsBUSET, O; DECLERCQ, M; FOUAD RAHALI et al.International journal of circuit theory and applications. 1992, Vol 20, Num 3, pp 283-298, issn 0098-9886Article

A network comparison algorithm for layout verification of integrated circuitsBARKE, E.IEEE transactions on computer-aided design of integrated circuits and systems. 1984, Vol 3, Num 2, pp 135-141, issn 0278-0070Article

Layout optimization of shapeable components with extended pattern search applied to transmission designYIN, Sn; CAGAN, Jonathan; HODGES, Peter et al.Journal of mechanical design (1990). 2004, Vol 126, Num 1, pp 188-191, issn 1050-0472, 4 p.Article

Standards for keyboard layout―the origins and scope of ISO/IEC 9995PATERSON, B.ICL technical journal. 1992, Vol 8, Num 2, pp 316-331, issn 0142-1557Article

Calcul de la précision des travaux de piquetage et des canevas de chantierZHUKOV, B. N.Izvestiâ vysših učebnyh zavedenij. Geodeziâ i aerofotosëmki. 1983, Num 2, pp 41-46, issn 0536-101XArticle

Layout replacement for sliced architectureLARMORE, L. L; GAJSKI, D. D; WU, A. C.-H et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 1, pp 102-114, issn 0278-0070Article

A hierarchy-driven amalgamation of standard and macro cellsREINGOLD, E. M; SUPOWIT, K. J.IEEE transactions on computer-aided design of integrated circuits and systems. 1984, Vol 3, Num 1, pp 3-11, issn 0278-0070Article

Symbolic layout compaction under conditional design rulesCHUNG-KUAN CHENG; XIAOTIE DENG; YUH-ZEN LIAO et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 4, pp 475-486, issn 0278-0070Article

On internal-external layoutsTOLLIS, I. G.IEEE transactions on circuits and systems. 1989, Vol 36, Num 1, pp 154-156, issn 0098-4094, 3 p.Article

Sélection des fondations de ponts pour s'accorder aux conditions géologiques et topographiquesOSHIMA, K.Tsuchi to kiso. 1986, Vol 34, Num 9, pp 9-12, issn 0041-3798Article

Removing edge-node intersections in drawings of graphsWEI LAI; EADES, Peter.Information processing letters. 2002, Vol 81, Num 2, pp 105-110, issn 0020-0190Article

A parallel algorithm for channel routing problemsFUNABIKI, N; TAKEFUJI, Y.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 4, pp 464-474, issn 0278-0070Article

Circuit placement on arbitrarily shaped regions using the self-organization principleSUNG-SOO KIM; CHONG-MIN KYUNG.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 7, pp 844-854, issn 0278-0070Article

TILT, a technology independent layout toolRIEM-VIS, R; MALIKI, G; PELLANDINI, F et al.AGEN-Mitteilungen. 1992, Num 55, pp 29-38, issn 1016-1554Conference Paper

Standortplanung und geodätische Projekte von Industrieanlagen = Implantation et étude de géodésie d'usinesODOR, K.Periodica polytechnica. Civil engineering (Print). 1983, Vol 27, Num 3-4, pp 157-169, issn 0553-6626Article

Graph layout for displaying data structuresWADDLE, Vance.Lecture notes in computer science. 2001, pp 241-252, issn 0302-9743, isbn 3-540-41554-8Conference Paper

Cell-based layout techniques supporting gate-level voltage scaling for low powerYEH, Chingwei; KANG, Yin-Shuin.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 5, pp 629-633, issn 1063-8210Conference Paper

REX «Guise II» Métrologie de chantier. 118 logements PLA à Dijon (21): Rapport de suivi/évaluation = REX «Guise II». Site metrology. 118 local authority flats in Dijon: Progress/assessment reportSALAGNAC, J.L.1997, 68 p.Report

On the effect of floorplanning on the yield of large area integrated circuitsKOREN, Z; KOREN, I.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 1, pp 3-14, issn 1063-8210Conference Paper

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